1. Field of the Invention
The present invention relates generally to programmable interconnect systems, and more particularly, to methods and systems using programmable interconnect chips and programmable gate arrays, user components, or the like for the purpose of conducting emulation, prototyping, and execution of new electrical circuit designs.
2. Description of the Prior Art
In order to verify a new electrical circuit design by performing system level tests, programmable interconnect systems with programmable interconnect chips (PICs) provide a quick and inexpensive alternative over prototyping the new circuit design on a custom built printed circuit board or in actually making the integrated circuit. New circuit designs can be quickly implemented on a programmable interconnect system where the PICs can be specifically configured to route signals to and from user components in accordance with the circuit design.
One such programmable interconnect system is disclosed in a U.S. Pat. No. 5,036,473, issued on Jul. 30, 1991 to Butts et al. In that system, referring to FIG. 3 of that patent, each logic chip, also referred to as field programmable gate arrays (FPGA), is surrounded by eight routing chips (or PICs) in order to provide maximum flexibility for connectivity among the FPGA chips. The layout of this design is fairly simple and inexpensive because every PIC only connects to its physically adjacent PICs. However, this architecture does not utilize the routing resources in an efficient manner. For example, one of the routing traces in the figure passes through seven of the routing chips and uses fourteen pins, significantly over utilizes the routing resources of the programmable interconnect system.
Another design is illustrated in FIG. 6 of that patent referred to as a partial crossbar interconnect system. In such a system, each logic chip is connected to every crossbar chip (or PIC chip). Although this is a fair design, the architecture requires that each PIC chip connects to each logic chip. When the number of PIC chips increases, the traces for connecting a PIC chip to a remote logic chip would traverse across the circuit board in a highly complicated layout and thereby resulting in a high manufacturing cost. Furthermore, there is no signal path available from one crossbar chip to another crossbar chip.
Another programmable interconnect system is described in a U.S. Pat. No. 5,377,124, issued on Dec. 27, 1994 to Moksen. In that disclosure, referring to FIG. 3b of that patent, a global interconnect architecture is illustrated where each PIC (311-1 to 311-4) is connected to each of the other PICs by means of dedicated conductive 2-branch buses, each containing a selected number of conductive lines (such as 8 or 16 conductive lines). User components in the architecture would be selectively placed adjacent to each PIC and connected to them. This architecture is good for the system where there are a limited number of PICs. For a system having a large number of PICs, this architecture becomes drastically complicated where the buses crisscross in a complex network of interconnects such that an implementation of a large scale version of this architecture would require many additional PCB layers thereby increasing the cost of such interconnect system.
Other architectures are illustrated by FIGS. 3a, 3c, and 3d of that patent. These architectures demonstrate the various possible manners for connecting PICs via buses, and each of these architectures has its particular advantages and weaknesses. For example, the architecture illustrated in FIG. 3a is a less costly architecture but is also a more restrictive architecture than that of FIG. 3b. The PICs are still connected through dedicated 2-branch buses but there may not be a bus between any two PICs to connect two user components. Thus, a signal may need to pass through more than two PICs and be further delayed in the process. For the architecture illustrated by FIG. 3c, although such a common non-dedicated global bus simplifies the interconnections of the PICs, a bus protocol is necessary to manage the conflict calls from the various PICs. With the protocol and conflict management system in place, the performance of such a system is low due to the fact that conflict resolution of bus requests from the various PICs requires additional cycle time thereby slowing down the entire system. Likewise, with regard to the architecture illustrated by FIG. 3d, the center PIC has to be configured in such a manner to manage the communication protocol between it and the surrounding PICs. The addition of such protocol again slows the performance of the system, and the center PIC can easily become the performance bottle neck.
Finally, another programmable interconnect system of interest is described in a U.S. patent, Ser. No. 5,414,638, issued May 9, 1995 to Verheyen et al. Referring to FIG. 2 of that patent, an architecture using two levels of PICs, a global PIC level and a local PIC level, is illustrated. In this system, a signal would have to pass through a local PIC, a global PIC, and another local PIC in order to complete a connection. For a signal to travel from a local PIC to another local PIC, a two level delay is introduced which results in low speed performance.
Overall, current programmable interconnect systems, including the systems described above, fail to recognize some of the key characteristics in circuit designs and the cost factors involved in the manufacturing of a programmable interconnect system.